VMIC-5565

Product Details

The VMIPCI-5565 features a single PCI interrupt output (INTA#), where one or more events on the VMIPCI-5565 can trigger the interrupt. These events' sources can be individually enabled and monitored through various registers.

Here's an overview of the interrupt circuitry and its tiers:

First Tier Interrupts:

The first tier of interrupts is managed by the PLX device through the Local Configuration Register's INTCSR register at offset . The optional sources for monitoring these interrupts include:

Local-to-PCI Doorbell register

Messaging Outbound Post Queue not empty

Master/Target Abort Status condition

256 consecutive PCI Retries as PCI bus master

DMA Ch 0 Done/Terminal Count

DMA Ch 1 Done/Terminal Count

Local Interrupt Input (LINTi#)

The usage of some first-tier sources (1) and (2) is limited in the VMIPCI-5565. Sources (3) and (4) are used based on the host system's requirements. Sources (5) and (6) are utilized during DMA cycles and require further configuration in the DMA registers. The final first-tier interrupt source (7) is the Local Interrupt Input (LINTi#), which serves as a physical input to the PLX device. All secondary tier interrupts pass through LINTi#.

Second Tier Interrupts:

Second-tier interrupts include operational faults and four network interrupts. These interrupts are selected and monitored through the Local Interrupt Status Register (LISR) and the LIER (RFM Control and Status Registers).

For detailed descriptions and configurations of these registers, refer to the Programming section of the documentation. A block diagram of the main interrupt circuitry is provided for reference.